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ds04-29128-1e fujitsu semiconductor data sheet copyright?2007 fujitsu li mited all rights reserved spread spectrum clock generator mb88153a mb88153a-100/101/110/111 description mb88153a is a clock generator for emi (electro magnetic interference) reduction. the peak of unnecessary (emi) can be attenuated by making the oscilla tion frequency slightly modulate peri odically with the internal modulator. it corresponds to both of the center spread which mo dulates input frequency as mi ddle centered and down spread which modulates so as not to exceed input frequency. feature ? power down pin : 10 a (typ-sample) consumption current at power down input frequency : 16.6 mhz to 134 mhz output frequency : 16.6 mhz to 134 mhz (one-fold input frequency) modulation rate can select from 0.5 % , 1.5 % ? 1.0 % or ? 3.0 % . (for center spread / down spread.) modulation clock output duty : 40 % to 60 % modulation clock cycle-cycle jitter : less than 100 ps low current consumption by cmos proces s : 4.0 ma (24 mhz : typ-sample, no load) power supply voltage : 3.3 v 0.3 v operating temperature : ? 40 c to + 85 c package : 8-pin sop
mb88153a 2 product lineup mb88153a has four kinds of modulation rate an d modulation type (center spread/down spread). pin assignment pin description product modulation rate modulation type mb88153a-100 ? 1.0 % down spread mb88153a-101 ? 3.0 % MB88153A-110 0.5 % center spread mb88153a-111 1.5 % pin name i/o pin no. description ckin i 1 clock input pin v dd ? 2 power supply voltage pin v ss ? 3gnd pin ckout o 4 modulated clock output pin ?l? output at power down ens i 5 modulation enable setting pin freq1 i 6 frequency setting pin freq0 i 7 frequency setting pin (with pull-up resistor) xpd i 8 power down pin (with pull-up resistor) power down at ?l? input 1 2 3 4 8 7 6 5 ckin v dd v ss ckout xpd freq0 freq1 ens top view mb88153a fpt-8p-m02
mb88153a 3 i/o circuit type (continued) pin circuit type remarks ckin, ens, freq1 cmos hysteresis input freq0 cmos hysteresis input with pull-up resistor 50 k ? (typ) xpd cmos hysteresis input with 50 k ? + 800 k ? (typ) pull-up resistors note : if ?l? is input to xpd when the xpd function is selected, 50 k ? pull-up resistor is disconnected. 50 k ? 50 k ? 800 k ?
mb88153a 4 (continued) pin circuit type remarks ckout cmos output ?l? output at power down
mb88153a 5 handling devices preventing latch-up a latch-up can occur if, on this de vice, (a) a voltage higher than v dd or a voltage lower than v ss is applied to an input or output pin or (b) a voltage hi gher than the rating is applied between v dd pin and v ss pin. the latch-up, if it occurs, significantly increases the power supply cu rrent and may cause thermal destruction of an element. when you use this device, be very careful not to exceed the maximum rating. handling unused pins do not leave an unused input pin open, since it ma y cause a malfunction. handle by, using a pull-up or pull-down resistor. unused output pin should be opened. power supply pins please design connecting the power supply pin of this devi ce by as low impedance as possible from the current supply source. we recommend connecting electrolytic capacitor (about 10 f) and the ceramic capacitor (about 0.01 f) in parallel between v ss pin and v dd pin near the device, as a bypass capacitor. clock i/o circuit noise near the ckin pin may cause the device to malfun ction. design the printed circuit board so that the wiring for the clock input does not intersect any other wiring. please pay attention so that an overshoot and an undershoot do not occu r to an input clock of ckin pin. design the printed circuit board that surro unds the ckin and ckout pins with ground.
mb88153a 6 block diagram v dd v ss ckout pll b lock mod u l a tion clock o u tp u t xpd 8 2 4 7 6 5 1 3 freq1 ckin freq0 en s 1 ? m 1 ? n 1 ? l idac ico clock input phase compare v/i conversion loop filter reference clock modulation logic modulation clock output modulation rate setting/ modulation enable setting mb88153a pll block frequency setting frequency setting modulation enable setting power down frequency setting a glitchless idac (current output d/a converter) provid es precise modulation, thereby dramatically reducing emi. charge pump
mb88153a 7 pin setting when changing the pin setting, the stab ilization wait time for the modulati on clock required. the stabilization wait time for the modulation clock takes the maximum value of lock-up time in ? electrical character- istics ? ac characteristics?. ens modulation enable setting note : spectrum does not spread when ?l? is set to ens. the clock with low jitter can be obtained. freq0, freq1 frequency setting note : it is set according to the frequency of the clock in put to the device. set freq0 pin to ?h? for the pin opened because freq0 pin has pull-up resistor. xpd power down setting note : when ?l? is set to xpd pin, the power down operati on is implemented and ?l? is output to ckout pin. when ?h? is input to xpd pin or xpd pin is opened, nor mal operation is implemented because the xpd pin has pull-up resistor. ens modulation l no modulation h modulation freq0 freq1 input frequency range l l 16.6 mhz to 40 mhz l h 66 mhz to 134 mhz h l 33 mhz to 67 mhz h h 40 mhz to 80 mhz xpd power down l power down h normal operation
mb88153a 8 ? center spread spectrum is spread (modulated) by centering on the input frequency. ? down spread spectrum is spread (modulated) below the input frequency. ? 1.5% + 1.5% radiation level input frequency frequency center spread example of 1.5 % modulation rate 3.0 % modulation width ? 3.0 % radiation level input frequency frequency down spread example of ? 3.0 % modulation rate 3.0 % modulation width
mb88153a 9 absolute maximum ratings * : the parameter is based on v ss = 0.0 v. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit min max power supply voltage* v dd ? 0.5 + 4.0 v input voltage* v i v ss ? 0.5 v dd + 0.5 v output voltage* v o v ss ? 0.5 v dd + 0.5 v storage temperature t st ? 55 + 125 c operation junction temperature t j ? 40 + 125 c output current i o ? 14 + 14 ma overshoot v iover ? v dd + 1.0 (t over 50 ns) v undershoot v iunder v ss ? 1.0 (t under 50 ns) ? v v dd v ss input pin overshoot/undershoot t under 50 ns t over 50 ns v iover v dd + 1.0 v v iunder v ss ? 1.0 v
mb88153a 10 recommended operating conditions (v ss = 0.0 v) warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter sym- bol pin conditions value unit min typ max power supply voltage v dd v dd ? 3.0 3.3 3.6 v ?h? level input voltage v ih ckin, ens, freq0, freq1, xpd ? v dd 0.8 ? v dd + 0.3 v ?l? level input voltage v il ckin, ens, freq0, freq1, xpd ? v ss ? v dd 0.2 v input clock duty cycle t dci ckin 16.6 mhz to 134 mhz 40 50 60 % operating temperature ta ?? ? 40 ? + 85 c ckin t a t b 1.5 v input clock duty cycle (t dci = t b /t a )
mb88153a 11 electrical characteristics dc characteristics (ta = ? 40 c to + 85 c, v dd = 3.3 v 0.3 v, v ss = 0.0 v) ac characteristics (ta = ? 40 c to + 85 c, v dd = 3.3 v 0.3 v, v ss = 0.0 v) (continued) parameter symbol pin conditions value unit min typ max output voltage v oh ckout ?h? level output i oh = ? 4 ma v dd ? 0.5 ? v dd v v ol ckout ?l? level output i ol = 4 ma v ss ? 0.4 v output impedance z o ckout 16.6 mhz to 134 mhz ? 45 ?? input capacitance c in ckin, ens, freq0, freq1, xpd ta = + 25 c, v dd = v i = 0.0 v, f = 1 mhz ?? 16 pf load capacitance c l ckout 16.6 mhz to 67 mhz ?? 15 pf 67 mhz to 100 mhz ?? 10 100 mhz to 134 mhz ?? 7 input pull-up resistance r pue freq0 v il = 0.0 v 25 50 200 k ? r pup xpd 500 800 1200 power supply current i cc v dd no load capacitance at 24 mhz output ? 4.0 6.0 ma power down current ipd v dd input clock stopping ? 10 ? a parameter symbol pin conditions value unit min typ max input frequency f in ckin ? 16.6 ? 134 mhz output frequency f out ckout ? 16.6 ? 134 mhz output slew rate sr ckout load capacitance 15 pf 0.4 v to 2.4 v 0.4 ? 4.0 v/ns output clock duty cycle t dcc ckout 1.5 v 40 ? 60 % modulation frequency (number of input clocks per modulation) f mod (n mod ) ckout freq[1 : 0] = (00) fin/2640 (2640) fin/2280 (2280) fin/1920 (1920) khz (clks) freq[1 : 0] = (10) fin/4400 (4400) fin/3800 (3800) fin/3200 (3200) freq[1 : 0] = (11) fin/5280 (5280) fin/4560 (4560) fin/3840 (3840) freq[1 : 0] = (01) fin/8800 (8800) fin/7600 (7600) fin/6400 (6400)
mb88153a 12 (continued) (ta = ? 40 c to + 85 c, v dd = 3.3 v 0.3 v, v ss = 0.0 v) note : the modulation clock stabilization wait time is requ ired after the power is turned on, the ic recovers from power saving, or after freq (frequency range) or en s (modulation on/off) setting is changed. for the modulation clock stabilization wait time, assign the maximum value for lock-up time. < definition of modulation frequency and number of input clocks per modulation > mb88153a contains the modulation period to realize the efficient emi reduction. the modulation period f mod depends on the input frequenc y and changes between f mod (min) and f mod (max) . furthermore, the average value of f mod equals the typical value of the electrical characteristics. parameter symbol pin conditions value unit min typ max lock-up time t lk ckout 16.6 mhz to 80 mhz ? 25 ms 80 mhz to 134 mhz ? 38 cycle-cycle jitter t jc ckout no load capacitance, ta = + 25 c, v dd = 3.3 v ?? 100 ps-rms t f mod (min) f mod (m a x) t modulation wave form clock count n mod (max) f (output frequency) clock count n mod (min)
mb88153a 13 output clock duty cycle (t dcc = t b /t a ) input frequency (f in = 1/t in ) output slew rate ( sr ) cycle-cycle jitter ckout 1.5 v t a t b 0.8 v dd t in ckin 2.4 v 0.4 v t f t r ckout note : sr = (2.4 ? 0.4) /t r , sr = (2.4 ? 0.4) /t f t n+1 t n ckout note : cycle-cycle jitter is defined the differen ce between a certain cycle and immediately after (or, immediately before) .
mb88153a 14 modulation wave form f mod ? 1.5 % + 1.5 % f mod ? 1.0 % ? 0.5 % ? 1.5 % modulation rate, example of center spread ? ? 1.0 % modulation rate, example of down spread ckout output frequency ckout output frequency frequency at modulation off frequency at modulation off time time
mb88153a 15 lock-up time if the xpd pin is fixed at the ?h? leve l, the maximum time after the power is turned on until the set clock signal is output from ckout pin is (the stabilization wait time of input clock to ckin pin) + (the lock-up time ?t lk ?). for the input clock stabilization time, check the characte ristics of the resonator or oscillator used. when xpd pin controls the power-down, stable clock is output from ckout pin after becoming xpd pin = ?h? level (in the maximum after lock-up time (t lk ) ). (continued) 3.0 v v dd ckin xpd v ih v ih ckout setting pin freq0, freq1, ens external clock stabilization wait time t lk (lock-up time ) v ih v ih 3.0 v v dd ckin xpd ckout setting pin freq0, freq1, ens external clock stabilization wait time t lk (lock-up time )
mb88153a 16 (continued) when ens pin is controlled for enable modulation, it is necessary for the stably clock output from ckout pin to wait lock-up time (t lk ) . note : in the following cases, it is necessary for the stab ly clock output from ckout pin, to wait lock-up time (t lk ) . - after releasing power-down - when you change other terminal settings output frequency, output clock duty cycle, modulati on frequency, and cycle-cycle jitter are not guaranteed until the output clock is stable. it is recommended to ta ke procedure to release of reset after. lock-up time (t lk ) on the device using the modulation clock or etc. v il v ih v ih ckin xpd ens ckout t lk (lock-up time ) t lk (lock-up time )
mb88153a 17 interconnection circuit example 1 2 3 4 8 7 6 5 mb88153a freq0 xpd c 1 c 2 freq1 ens r 1 v dd ckin v ss ckout + c 1 : capacitor of 10 f or higher c 2 : capacitor of approximately 0.01 f (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device) r 1 : impedance matching resistor for a circuit on a board
mb88153a 18 spectrum example characteristics the condition of the examples of the charac teristic is shown as follows: input frequency = 20 mhz (output frequency = 20 mhz), use for mb88153a-111. power-supply voltage = 3.3 v, none load capacity. modulation rate = 1.5 % (center spread). spectrum analyzer hp4396b is connected with ckou t. the result of the measurement with rbw = 1 khz ( at t use for ? 6 db ) . ch b spectrum 10 db /ref 0 dbm avg 4 rbw# 1 kh z vbw 1 kh z att 6 db center 20 mh z swp 2.505 s span 4 mh z no modulation ? 8.86 dbm 1.5 % modulation ? 26.54 dbm
mb88153a 19 ordering information part number modulation rate modulation type package remarks mb88153apnf-g-100-jne1 ? 1.0 % down spread 8-pin plastic sop (fpt-8p-m02) mb88153apnf-g-101-jne1 ? 3.0 % down spread mb88153apnf-g-110-jne1 0.5 % center spread mb88153apnf-g-111-jne1 1.5 % center spread mb88153apnf-g-100-jnefe1 ? 1.0 % down spread 8-pin plastic sop (fpt-8p-m02) emboss taping (ef type) mb88153apnf-g-101-jnefe1 ? 3.0 % down spread mb88153apnf-g-110-jnefe1 0.5 % center spread mb88153apnf-g-111-jnefe1 1.5 % center spread mb88153apnf-g-100-jnere1 ? 1.0 % down spread 8-pin plastic sop (fpt-8p-m02) emboss taping (er type) mb88153apnf-g-101-jnere1 ? 3.0 % down spread mb88153apnf-g-110-jnere1 0.5 % center spread mb88153apnf-g-111-jnere1 1.5 % center spread
mb88153a 20 package dimension please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 8 -pin pl as tic s op le a d pitch 1.27 mm p a ck a ge width p a ck a ge length 3 .9 5.05 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.75 mm max weight 0.06 g 8 -pin pl as tic s op (fpt- 8 p-m02) (fpt- 8 p-m02) c 2002 fujit s u limited f0 8 004 s -c-4-7 1.27(.050) 3 .900. 3 0 6.000.40 .199 ?.00 8 +.010 ?0.20 +0.25 5.05 0.1 3 (.005) m (.154.012) (.2 3 6.016) 0.10(.004) 14 5 8 0.440.0 8 (.017.00 3 ) ?0.07 +0.0 3 0.22 .009 +.001 ?.00 3 45 ? 0.40(.016) "a" 0~ 8 ? 0.25(.010) (mo u nting height) det a il s of "a" p a rt 1.550.20 (.061.00 8 ) 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.150.10 (.006.004) ( s t a nd off) 0.10(.004) * 1 * 2 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * 1 : the s e dimen s ion s incl u de re s in protr us ion. note 2) * 2 : the s e dimen s ion s do not incl u de re s in protr us ion. note 3 )pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 4) pin s width do not incl u de tie ba r c u tting rem a inder.
mb88153a f0706 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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